Intel Panther Lake Shows Strong Linux CPU Performance & Power Efficiency With Core Ultra X7 358H Benchmarks

For those that have been very eager to hear about the Intel Core Ultra Series 3 “Panther Lake” performance on Linux, today’s the day! Last Thursday the MSI Prestige 14 Flip AI+ Evo laptop arrived that is powered by the Core Ultra X7 358H. Here is a look at how that Intel Core Ultra X7 358H competes for performance and power efficiency against a wide range of other laptops on an up-to-date Linux software stack in with around 300 benchmarks.

[$] The future for Tyr

The

team
behind

Tyr
started 2025 with little to show in our quest to
produce a Rust GPU driver for Arm Mali hardware, and by the end of the
year, we were able to play SuperTuxKart (a 3D open-source racing
game) at the Linux Plumbers Conference (LPC). Our prototype was a joint
effort between Arm, Collabora, and Google; it ran well for the duration
of the event, and the performance was more than adequate for players.
Thankfully, we picked up steam at precisely the right moment: Dave
Airlie just

announced
in the Maintainers Summit that the DRM subsystem
is only “about a year away” from disallowing new drivers written in C
and requiring the use of Rust. Now it is time to lay out a
possible roadmap for 2026 in order to upstream all of this work.

Linux Dropping SMC TCP ULP Support For Being “Fundamentally Broken”

Merged four years ago to the Linux kernel networking subsystem’s Shared Memory Communications (SMC) code was TCP Upper Layer Protocol (ULP) support for allowing applications to replace TCP with the SMC protocol in-place as a transparent replacement. Except for the next kernel cycle it’s set to be reverted after realizing it’s “fundamentally broken.”..

Reworked NTFS Linux Driver Posted With More Improvements & Fixes

Announced back in October was NTFS Plus as a new Linux driver for NTFS based on the former NTFS kernel driver prior to Paragon Software contributing the NTFS3 driver code. The intent with this new driver is for better performance. more features, public user-space utilities around it, and all-around a nice step forward for those reliant on this Microsoft file-system. Out this week is the sixth iteration of this remade NTFS driver…

Security Researchers Find Current RISC-V CPU Implementations Coming Up Short

While many open-source enthusiasts like to flaunt RISC-V as not having the security challenges as x86_64 CPUs have seen over the past several years with various speculative execution / side-channel attacks and arguing for the benefits of an open-source ISA in stronger security, in practice it’s not so clear-cut. Security researchers at Germany’s CISPA Helmholtz Center for Information Security have found current RISC-V CPU implementations coming up short for their actual security…

[$] Modernizing swapping: introducing the swap table

The kernel’s swap subsystem is a complex and often unloved beast. It is
also a critical component in the memory-management subsystem and has a
significant impact on the performance of the system as a whole. At the
2025 Linux Storage, Filesystem, Memory-Management and BPF Summit, Kairui
Song outlined a plan to simplify and
optimize the kernel’s swap code. A first installment
of that work
, written with help from Chris Li, was merged for the 6.18
release. This article will catch up with the 6.18 work, setting the stage
for a future look at the changes that are yet to be merged.

Loongson 3B6000 Benchmarks: How China’s LoongArch CPU Compares To AMD Zen 5, Intel Arrow Lake & Raspberry Pi 5

Recently I finally got my hands on a LoongArch processor, the ISA developed by China’s Loongson Technology as an evolution from their earlier use of the MIPS64 ISA and inspired by RISC-V and other modern ISAs. The Loongson-3B6000 features 12 cores / 24 threads with dual channel DDR4 ECC memory support. Here is a look at how that latest-generation LoongArch desktop processor compares to the current generation AMD Zen 5 and Intel Arrow Lake desktop processors under Linux. Plus also tossing in the Raspberry Pi 5 (Raspberry Pi 500+) for an ARM reference point.