Arm this week introduced its Arm Total Design initiative, which is aimed at accelerating development of custom datacenter-oriented system-on-chip (SoC) designs using Neoverse Compute Subsystems (CSS). The collaborative ecosystem unites various developers in a bid to speed up time-to-market and reduce development costs of custom SoCs for AI, cloud, and high-performance computing markets. ATD promises to enable development of datacenter processors that will offer formidable competition for x86 CPUs.

The Arm Total Design ecosystem is a conglomerate of ASIC design houses, IP vendors, EDA tool providers, foundries, and firmware developers that is aimed to facilitate rapid and cost-efficient delivery of custom silicon for datacenters based on Arm Neoverse cores for AI, HPC, cloud, and networking workloads. The ecosystem provides preferential access to Neoverse CSS to its partners, fostering innovation, and facilitating faster time-to-market strategies, while also lowering development costs.

The initiative aims to harness collective industry expertise at every stage of custom SoC development, thereby promoting the broad availability of specialized, Arm Neoverse-based solutions. 

Central to this initiative is the delivery of pre-integrated, validated IP and EDA tools, courtesy of collaborative efforts from partners such as Cadence, Rambus, and Synopsys. Such strategic collaborations are instrumental in speeding up silicon design process as it simplifies incorporation of essential components like memory, security, and various peripherals.

In addition to the abovementioned companies, Arm Total Design leverages design services prowess of such companies ADTechnology, Alphawave Semi, Broadcom, Capgemini, Faraday, Socionext, and Sondrel. These companies bring their expertise to the table, providing robust support to the ecosystem given their experience with Neoverse CSS as well as other Arm IPs and technologies.

Since the expected future of datacenter processors is multi-chiplet, the Arm Total Design ecosystem not only makes custom chips more accessible, but also poised to support AMBA CHI C2C, and UCIe standards. Intel Foundry Services and TSMC also participate in the Arm Total Design ecosystem bringing in leading-edge process technologies and advanced packaging techniques.

Complementing the hardware-focused aspects, the initiative also places a strong emphasis on commercial software and firmware support for Neoverse CSS, drawing upon the specialized contributions from AMI.

On paper, Arm Total Design emerges as a major alliance that could significantly alter the landscape of custom datacenter silicon development. By combining a diverse spectrum of industry leaders under one roof, it promises a seamless and efficient pathway towards realizing the potentials of Neoverse CSS. This collaborative venture aspires to unlock new levels of performance and features for AI, edge, and HPC SoCs based on the Arm technology, offering a decidedly more group-oriented approach to chip design than the vertically integrated strategies employed by industy heavyweights such as Intel and AMD.

Source: AnandTech – Arm Total Design to Facilitate Development of Custom Datacenter SoCs

As part of a broad collaborative agreement with Google, Qualcomm this week said that that it will be adopting the RISC-V instruction set architecture (ISA) for a future Snapdragon Wear platform. Working together, the two companies will be bootstrapping a RISC-V ecosystem for Wear OS devices, with Qualcomm providing the hardware while Google expands its wearables OS and associated ecosystem of tools to support the new processor architecture.

Qualcomm’s Wear processors have been the de facto chip of choice for Wear OS devices since the launch of Google’s wearables platform almost a decade ago, with Qualcomm employing multiple generations of Arm CPU designs. This makes Qualcomm’s decision to develop a RISC-V wearables SoC especially significant, as it not only represents one of the highest profile adoptions of RISC-V in a consumer platform to date, but it means that, depending on Qualcomm’s specific product plans, this could see the overall Wear OS market make a hard turn from Arm to RISC-V in relatively short order.

As laid out in the relatively brief announcement from Qualcomm, the company will focus on development of RISC-V-based hardware suitable for wearable devices. While the company isn’t disclosing detailed technical specifications of their in-development products, given the company’s significant chip-design background, this likely includes customized RISC-V general purpose cores as well as sensors.

Notably here, the announcement is for “a RISC-V based wearables solution,” rather than a complete pivot to RISC-V with multiple solutions. Wearables as a whole are a much smaller market than smartphones, so Qualcomm has historically not offered a particularly deep lineup of hardware – meaning that even one chip is significant. Still, this also means that Qualcomm is not formally dropping Arm from its Snapdragon Wear platform at this time.

Qualcomm’s decision to embrace RISC-V for a future wearables SoC is significant news for the up-and-coming ISA, as this marks one of the highest profile adoptions of RISC-V in consumer gear to date. The open standard ISA has seen success over the last several years in the microcontroller market, with chip vendors adopting RISC-V CPU cores – often in place of Arm Cortex-M designs – as a means of having more control over their CPU core designs, and avoid paying ISA royalties in the process. Conversely, RISC-V has seen very limited adoption in the application processor space thus far, owing to the more complex chip designs and the overall smaller market. So Qualcomm’s plans to use RISC-V in their Snapdragon Wear platform, which has traditionally been based on Arm Cortex-A designs, marks a significant milestone for the adoption of RISC-V into higher-performing mobile devices.

Similarly, Google’s backing of the ISA by porting Wear OS to RISC-V is a major milestone on the software front. Bootstrapping a platform based on a new ISA is not just about the hardware, but the software as well, as there needs to be well-developed operating systems and applications to make the hardware useful. All of which requires significant tooling to enable that development. Google, for its part, is no stranger to embracing multiple ISAs – Android has long supported Arm, x86, and even MIPS – and the company already announced earlier this year that they’re working to make RISC-V a “tier-1” platform for Android, so the company’s efforts with Wear OS will go hand-in-hand with that.

Between the two companies, Google and Qualcomm essentially make up the software and hardware backend of the Wear OS ecosystem. Google’s Wear OS, in turn, is used by a range of popular smart watches, including those from Samsung, Fossil Group, Motorola, and Casio.

“Qualcomm Technologies have been a pillar of the Wear OS ecosystem, providing high performance, low power systems for many of our OEM partners,” said Bjorn Kilburn, GM of Wear OS by Google. “We are excited to extend our work with Qualcomm Technologies and bring a RISC-V wearable solution to market.”

Meanwhile, the decision to use RISC-V for wearables also has the potential to be a big change for the business side of Qualcomm. The company is current butting heads with Arm over licensing and royalty rates, particularly in regards to their acquired Nuvia IP. That relationship has already devolved to lawsuits, including Arm looking to block Qualcomm’s use of Nuvia-designed Arm CPU cores.

In short, swapping out Arm for RISC-V would allow Qualcomm to do away with paying royalties to Arm for Snapdragon Wear chips. The current royalties aren’t thought to be extravagant – Qualcomm is using Cortex-A53 here – but a penny saved is a penny booked for Qualcomm’s quarterly earnings. If nothing else, the very public announcement about the development of a RISC-V Snapdragon Wear SoC can be considered a shot across Arm’s bow, as a reminder that Qualcomm could eventually do the same thing with bigger and higher royalty bearing chips.

“We are excited to leverage RISC-V and expand our Snapdragon Wear platform as a leading silicon provider for Wear OS,” said Dino Bekis, vice president and general manager, Wearables and Mixed Signal Solutions, Qualcomm Technologies. ” Our Snapdragon Wear platform innovations will help the Wear OS ecosystem rapidly evolve and streamline new device launches globally.”

Source: AnandTech – Qualcomm Swaps Out Arm for RISC-V for Next-Gen Google Wear OS Devices