Last month the CXL Specification 1.0 was released as a future cache coherent interconnect that uses the PCIe 5.0 physical infrastructure but aimed to provide a breakthrough in utility as well as cache coherency. At the time, the to-be-defined consortium consisted of Intel and eight other founding members. Since the announcement, membership has grown from that initial nine to thirty three, including some important names in the industry.

Source: AnandTech – Compute Express Link (CXL): From Nine Members to Thirty Three